In the Spring of 2000, 11 students registered for K-State's EECE 690/890 (Digital Radio Microelectronics Design), an experimental course designed to teach RF integrated circuit design concepts while involving students in on-going research activities within our research group.  Class activities included traditional lectures, homeworks, and a midterm exam during the first half of the semester, followed by a design project during the second half.  The project required the entire class to work together toward a complex system design -- a complete Bluetooth-compatible receiver-on-a-chip.

Additional information on educational aspects of the course, including the syllabus, semester schedule, and project assignments can be found here.

Bluetooth is a new standard developed jointly by a host of companies to provide low-cost (< $5 OEM target), high data-rate (approx 1Mb/s), short-range (< 30meters) communication links between  consumer devices ranging from desktop and portable computers to cellular phones and digital cameras.  It operates in the 2.4 GHz ISM band using Frequency-Hopped Spread Spectrum (FHSS) FSK modulation, with transmit powers in the range of 0 dBm (1 milliwatt).  A complete Bluetooth product would include an RF transceiver, digital packet and protocol processing circuits, and an associated host interface.  Our goal in this first offering of the course was to develop the receiver portion of a Bluetooth RF transceiver - the circuits most resistant to integration.  Future classes and associated graduate students will add transmitter circuits to implement a complete RF physical-layer solution.

Students participating in the class were assigned to separate pieces of the overall design to allow the relatively large development project to be completed in a single semester.  Their circuits, together with layouts and simulation results are detailed in the following pages:

• Integrated Dipole Antenna
• Integrated Loop Antenna
• Q-Enhanced LNA and Local Oscillator
• Master-Slave Tuning Components
• 2.4 GHz Dynamic and 700 MHz Static Flip-Flops
• High Speed Programmable Divider, PFD, and Charge pump
• First and Second Image Reject Mixers
• Second LO
• 2-pole IF Channel-Select Filter
• IF amp and RSSI
• FSK demod and 3-pole Lowpass Filter

Our design is currently a prototype designed in Peregrine's 0.5um Silicon-on-Sapphire CMOS process using MOSIS scalable design rules at Lambda=0.1u and will be fabricated through MOSIS during 2Q00.   The final layout is shown below:

Click for larger image

The chip layout was completed on-schedule for a 1 May 2000 tapeout planned by MOSIS.  Unfortunately, the MOSIS schedule has been delayed and
we only recently received the die from this run.  We are currently in the process of testing our circuits.  Several circuit appear to be operational,
including the input matching network, the LNA (although at reduced gain due to a minor error), the divide-by-16 high-frequency prescaler, the
divide-by-N and associated phase-frequency-detector (PFD) and charge pump (CP), and the second LO.  Other circuits will be tested soon.

A follow-on class during Spring 2001 developed a companion transmitter to provide a complete Bluetooth RF chip.  Please see their
web page here for details !

• Companion transmitter circuits developed by Spring 2001 class.
• K-State's Fall 99 EECE696 (Intro to IC Design) course project page.
• 900 MHz Digital Cordless Phone designed by K-State students in Fall of 1998.
• K-State's Communication Circuits Laboratory
• Dr. Kuhn's Web Page

Last Update:  25 May 2001