CMOS Layout
The project layout was done using Magic for Linux. The chip will be fabricated using the Peregrine silicon on sapphire process. This is a 0.5um process. It utilizes an insulating substrate which has the effect of eliminating body effect in the FETs. A picture of the entire circuit layout appears below.
NOTE: Knowledge of CMOS layout in general and Magic in particular is necessary to interpret these diagrams.
Complete Circuit Layout
In order to make the above image easier to understand, it is broken down into its components.
I. The Gilbert Cell Mixer
The important nodes (see Section 4, "Simulation Results") are marked on the diagram.
II. The 3-pole filter
Again, the relevant nodes are marked on the diagram.
III. The Phase Shift Network
