Demodulator Schematic/Design
The demodulator block diagram below has three major sections that were implemented in this iteration of the design:
1) The Mixer,
2) The Filter,
3) The Phase Shift Network.
The mixer topology used in the demodulator is called a Gilbert cell mixer. It is used because it is fairly easy to implement in CMOS design (as opposed to passive mixer technologies such as a diode ring mixer). The schematic of the mixer section appears below.
In the above schematic:
1) The capacitors Cb1 and Cb2 provide coupling for the input (they are not actually implemented in this section of the layout, but are implemented in the 2nd IF Amplifier section).
2) The resistors Rb1,2,3,4, and 5 and the transistors Mb1,2, and 3 form the bias network for the input voltages (VIn and VSh, where VSh is a shifted version of VIn). The resistors R2,3,4, and 5 simply need to provide a large input impedance compared to the output impedance of the previous stage. The resistor R1 needs to provide a 0.8 volt drop with 50uA of current. The transistors Mb1,2, and 3 are diode connected and are sized for a drop of approximately 0.7 V each. This allows us to draw a 2.2 and a 1.5V bias from the same circuit.
3) Capacitors Cb1 and Cb2 provide coupling for the other mixer input. This input comes from the output of the phase-shift network.
4) Resistor Rm and transistors Mm1, 2, 3 form a current mirror. This mirror provides the current source for the entire circuit. It is designed to provide 50uA of current if the mirror transistor is the same size as the reference. If a multiple of 50uA is needed, another transistor is added in parallel. Although this could also be done by resizing the mirror transistor, this approach allows for matching to minimize the effect of process tolerances.
5) The transistors Mmx1,2,3,4,5, and 6 form the Gilbert Cell mixer. The transistors Mmx1,2,3, and 4 form the switching portion of the mixer and the transistors Mmx5 and 6 form the transconductor section. The switching transistors are sized so that they turn all the way on (i.e. enter the saturation or active region) when the input waveform is positive with respect to the bias voltage) and turn all the way off (i.e., enter the cutoff region) when the input waveform is negative with respect to the bias. The transconductor section is designed in the same way as for a normal differential amplifier.
6) The transistors Ml1 and 2 and the resistors Rl1 and 2 form an active load for the Gilbert cell mixer. This isn't really necessary for this part but it has advantages in the overall design. Using an active load here allows for matching of the active load sections throughout the circuit. This minimizes the effect of process tolerances and improves the bias stability of the circuit. The transistors are sized to provide the needed bias drop. The resistors control the gain of the mixer (along with the gm of the transconductor section).
The filter is a 3-pole low-pass filter using the direct replacement method (i.e., taking a basic normalized LPF design, replacing the inductor with an active inductor, and scaling to the desired impedance and frequency). An altered active inductor is used to accommodate a differential signal. The schematic of the LPF appears below.
In the above schematic:
1) The transistors Mm6,7,8,9, and 10 are mirror transistors for the current mirror in the mixer schematic.
2) The first transconductor is formed by Mf1 and 2 (and its active load - see description above). It acts as a buffer between the mixer and filter.
3) Rf1 and Cf1 are two of the devices used in the normalized lowpass filter (scaled to impedance and frequency).
4) The four transconductor cells (Mf2-10 and associated active loads) and capacitor Cf2 form the active inductor.
5) Rf2 and Cf3 are the final components of the normalized lowpass filter.
The phase shift network was actually designed by the engineer who designed the 2nd LO (see his section of the web page for more details and his copyright). I altered it to fit my own needs. It has a center frequency of 5.5MHz and bandwidth (where the phase shift is linear) of about 1MHz. It is basically a parallel RLC network where the inductor is an active inductor. Its schematic appears below.
In the above schematic:
1) The capacitors Cps1 and 2 are chosen so that their reactance is equal to the resistance of Rps1.
2) R is chosen to set a certain quality factor Q (and consequently, the bandwidth of the phase shift network). Note: I wanted a lower Q than the original, so I altered it to have a Q of about 4 and this changed both Rps1 and Cps1 and 2 from the original.
3) Cps3 and the active inductor (the two transconductor cells) set the center frequency of the phase shift network.