Copyright 2001, Kansas State University
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of Kansas State University and the students involved in the class.
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In the Spring of 2001, 7 students registered for K-State's EECE 690/890 (Digital Radio Microelectronics Design), an experimental course designed to teach RF integrated circuit design concepts while involving students in on-going research activities within our research group. Class activities included traditional lectures, homeworks, and a midterm exam during the first half of the semester, followed by a design project during the second half. The project required the entire class to work together toward a complex system design -- a complete Bluetooth-compatible transmitter-on-a-chip.
This transmitter is designed as a companion to the Bluetooth receiver designed and fabricated during the prior year. Details of the prior year's receiver design can be found here.
Bluetooth is a new standard developed jointly by a host of companies to provide low-cost (< $5 OEM target), high data-rate (approx 1Mb/s), short-range (< 30meters) communication links between consumer devices, ranging from desktop and portable computers to cellular phones and digital cameras. It operates in the 2.4 GHz ISM band using Frequency-Hopped Spread Spectrum (FHSS) FSK modulation, with transmit powers in the range of 0 dBm (1 milliwatt). A complete Bluetooth product would include an RF transceiver, digital packet and protocol processing circuits, and an associated host interface.
Our goal in this course is to develop the physical-layer RF portion of a Bluetooth transceiver A block diagram of the complete transceiver being developed is shown below. Items in red are being design this semester and are detailed in this web page. Items in green will be reused from the prior semester's class, while blue items will be modified versions of prior designs. Greyed items exist from the prior year's course, but will not be fabricated this semester. Finally, items in yellow will be added in the future.
Click here for a detailed block diagram of this semester's circuits and an overview of the system architecture.
Students participating in the class were divided into three teams and worked together to produce the transmitter circuits. Their designs, together with layouts and simulation results are detailed in the following pages:
Our design is being designed in Peregrine's 0.5um Silicon-on-Sapphire CMOS process using MOSIS scalable design rules at Lambda=0.1u. Layouts produced by the class teams will be combined into a padframe during the coming months and will be fabricated through MOSIS during 2Q01.
Test results will be posted here and documented in other publications after the fabricated chips are received later this year.
Last Update: 07 May 2001