Purpose
The frequency control code from the microcontroller contains 8 bits of digital data which are fed into the divide by N counter. The VCO frequency is controlled by 6 bits. When the VCO control bits set a certain frequency, for example 126 MHz, the divide by N counter needs to be set to divide by 126. As shown below, a 6-bit adder provides the translation, or mapping function, between the data needed for the divide by N counter and the VCO control data.
Design
To divide by N, the divide by N counter needs a number
that is 256-N at the input. If a divide by 119 is desired, the input
needs to be 137. As the desired divide by N number increases, the
number needed at the counter's input decreases. The VCO is set up
in a similar fashion. As the output frequency increases, the control
data needed to produce the output frequency decreases. A table
of the values needed for the divide by N counter and VCO control data is
shown below.
| Divide By N | 8-bit number needed for divide by N counter | 6-bit number needed by VCO |
| 119 | 137 = 10001001 | 100110 (119 Mhz) |
| 120 | 136 = 10001000 | 100101 (120 Mhz) |
| 121 | 135 = 10000111 | 100100 (121 Mhz) |
| 122 | 134 = 10000110 | 100011 (122 Mhz) |
| 123 | 133 = 10000101 | 100010 (123 Mhz) |
| 124 | 132 = 10000100 | 100001 (124 Mhz) |
| 125 | 131 = 10000011 | 100000 (125 Mhz) |
| 126 | 130 = 10000010 | 011111 (126 Mhz) |
| 127 | 129 = 10000001 | 011110 (127 Mhz) |
| 128 | 128 = 10000000 | 011101 (128 Mhz) |
| 129 | 127 = 01111111 | 011100 (129 Mhz) |
| 130 | 126 = 01111110 | 011011 (130 Mhz) |
| 131 | 125 = 01111101 | 011010 (131 Mhz) |
| 132 | 124 = 01111100 | 011001 (132 Mhz) |
| 133 | 123 = 01111011 | 011000 (133 Mhz) |
| 134 | 122 = 01111010 | 010111 (134 Mhz) |
Since the VCO and divide by N counter have the same relationship
with the control data, an adder was chosen to make the translation between
the two sets of control data. The frequency control code comes
from an off chip microcontroller, and feeds directly into the divide by
N counter. To get the corresponding code for the VCO control, and
offset is added to the 6 least significant bits of the divide by N data.
Since the VCO frequency and control data will most likely not match up
as indicated in the table above, this offset will have to be variable.
If it is assumed that the VCO control data and corresponding frequency
match up as shown above, the correct offset to add is 011101. An
example is shown below for the case where the VCO frequency needs to be
119 MHz and the divide by N number needs to be 119.
119 MHz desired, divide by N = 119.
Microcontroller sends 256-119 = 137 = 10001001
001001 6 least significant
bits of 10001001 (A5...A0)
+ 011101
Offset Bits (X5...X0)
100110 Data needed
at VCO control input for 119 MHz (B5...B0)
As mentioned earlier, the offset will need to be variable. For example, if the VCO control code for 119 MHz is really 100100 instead of 100110, the offset will be 2 less than it was for the example above.
The adder used is a 6-bit ripple carry adder. A gate level schematic of the circuit is shown below. Bits (A5...A0) represent the 6 least significant bits of the divide by N data, bits (X5...X0) represent the offset, and bits (B5...B0) represent the control data going to the VCO.
