Figure 1: The Bluetooth transmitter architecture.
A
Low Sensitivity Switched Capacitance VCO
Links to Team 3 members:
Charge Pump, Loop Filter, and Code Mapping
HF VCO and Power Amplifier
with T/R Switch
A
low sensitivity switched capacitance VCO is described along with its use in a
fully-integrated, student-designed Bluetooth transmitter. Using a switched capacitor method to tune
the VCO reduces the required sensitivity and tuning range of the VCO and
reduces the lock time of the PLL. An
open loop architecture is used for the transmitter and the low sensitivity VCO
reduces frequency drift usually associated with this architecture. MOSCAPs are used for the digital tuning and
design considerations for max to min capacitance ratio are discussed. Simulation results using HP EESof are shown.
The current push towards full integration of transceivers has lead to an increased demand of students who familiar with RFIC design. To fulfill this need, Kansas State University has had two recent course offerings in single chip transceiver design. The goal of these courses has been to design a Bluetooth transceiver in two semesters: a receiver in the first semester, a transmitter in the second. More information regarding this is available in [1] and on the web at http://www.eece.ksu.edu/vlsi/bluetooth.
The
transmitter architecture used is shown in Fig. 1. Bluetooth systems use Frequency Hopped Spread Spectrum (FHSS),
where the 1MHz bandwidth channels are changed 1600 times a second [2]. This system uses an open loop architecture,
where the PLL locks to the new channel, and then is opened during the
modulation of the data. Open loop
transmitters are prone to frequency drift due to fluctuations in the control
voltage across the capacitor in the loop filter [3]. Decreasing the sensitivity of the VCO can reduce the effect of
these fluctuations. The KSU transmitter
architecture uses a switched capacitance method to reduce the tuning range
required of the VCO, which means a lower sensitivity can be reached [4].
If
the VCO frequency jump is performed via a digital word before attempting to
lock the PLL, the amount of analog tuning required for this frequency change is
reduced. This allows the tuning range
of the VCO to be less and consequently its’ sensitivity is reduced [5]. Since the VCO frequency is close to the
channel of interest, the lock time of the PLL is reduced. The KSU transmitter architecture also uses
an upconversion step between the modulation of the data and the power
amplification to reduce the effect of frequency pulling. The VCO nominal frequency is 126MHz, while
the output of the power amplifier is at 2.4GHz. A problem encountered with direct launch architectures is that
the VCO frequency is the same as the output of the power amplifier, which leads
to frequency pulling if there is coupling between the power amplifier output
and the VCO.
The
sensitivity of the VCO is 1.25MHz/V for the data input, which results in the
nominal Bluetooth peak frequency deviation of 125kHz for a 100mV signal from
the 500kHz data smoothing filter. The
sensitivity of the analog frequency tuning is 1.5MHz/V for the PLL input. The VCO is also in an Automatic Level
Control (ALC) loop that compares the output amplitude of the transmitter with a
reference voltage, which in turn sets the output amplitude of the VCO. The VCO is set to the point at which it is
just oscillating in order to improve the spectral purity of its’ output and
predictability of its tuning steps.
Figure 1: The Bluetooth transmitter architecture.
The
block diagram of the VCO in Fig. 2 shows the principle of its’ operation. The VCO is based on a gm -C topology
where the resonator is formed using an active inductor. The input of the circuit formed by the gm cells is an inductance
value, which is dependent on gm
and C and is given by: L=C/gm
2.
Since
L depends on C, we can change this value by varying C. There are several ways
to accomplish a variable C, but in
this situation a discrete change in capacitance is desired. This can be achieved by an array of binary
weighted capacitors with several bits controlling them. Each channel in the VCO operating range has
a digital word associated with it, which is sent to the capacitor array to
cause a capacitance increment, which causes an increment in L and therefore a jump in
frequency. Since L also depends on gm,
varying the tail current of the gm cell can change the frequency of the
VCO. This analog tuning technique is
used to implement the low-sensitivity data and PLL control input.
The
VCO needs a negative resistance in the core to counter the resistance
associated with the active inductor.
Varying the cell’s tail current can change this negative resistance
value. The tail current is set by the
ALC so that the VCO is just past the value of negative resistance needed for
oscillation.
Figure 2: A block diagram of the VCO.
The
complete schematic is shown in Fig. 3.
The top gm cell is
implemented with differential analog control on the data input to reduce common
mode noise. The bottom gm cell receives its analog
control from the loop filter.
The
bottom cell’s gm value is
determined by the sum of the gm
s of the parallel FETs M9 and M10. The gm value of M9 is not varied,
while the gm value of M10
is controlled. A channel length of 1mm is
used for M10 to improve the variation of its’ gm value.
Increasing the tail current of M10 by increasing the gate to source
voltage of M8 causes an increase of the gm
of M10 and an overall increase in the gm
of the cell. This varies the value of
the active inductor and hence the frequency of the oscillation.
The
top gm cell uses
differential control with three pairs of FETs that are in parallel, except one
pair of the tuning FETs are cross-coupled.
This is done so that an increase in the difference between the gate to
source voltages of M3a and M3b causes a difference in the gm of the cross coupled FETs labeled M2a. This
difference in gm of the
FETs increases the gm of
the cell because of the cross coupling of the drains. The gm of
the cell is found by adding the gm of
M1 to the difference in the gm
of the cross coupled FETs.
The
cross-coupled pair M12a and M12b determines the negative resistance value seen
by the core. The negative resistance
value that this cell produces is given by:
R=-2/ gm.
Increasing
the value of gm after the
oscillation point has been reached moves the poles on the root locus of the
oscillator further into the right hand plane.
This eventually sends the oscillator into a nonlinear mode of operation
and the signal output of the VCO becomes distorted. In order to improve the spectrum of the output, the VCO is put in
an ALC loop, which sets the operating point of the VCO in the linear region. By varying M13, the amount of negative
resistance changes due to the changes in the gm of M12.
Figure 3: A full schematic of the VCO.
The
switched capacitors are implemented using the MOS capacitors (MOSCAP) available
in the 0.5mm Peregrine
Silicon-on-Sapphire process . Tying the
drain and source of a MOSFET together makes a MOSCAP. Since the MOSCAP is an active device, there is a difference in
the capacitance value attained between when the channel is formed and when
there is no channel formed. In order to
form a channel there has to be a gate to source voltage greater than a certain
threshold. The MOSCAPs are switched on
and off by an inverter comprised of M22 and M23 in Fig. 3. A low voltage applied to the input of the
inverter brings the drain and source of the MOSCAP to a high voltage and turns
the MOSCAP off, or to the minimum capacitance value. Applying a high voltage to the input of the inverter pulls the
drain and source of the MOSCAPs to a low voltage, turning the MOSCAPs on to
their maximum capacitance value.
Another
factor in the design of the MOSCAP is that in order to be useful, there should
be a sizeable difference between the max and min capacitance values. It can be seen from Fig. 4 that the length
of the gate of the MOSCAP determines this ratio of max to min capacitance
value. The min capacitance value is
reached when there is no channel formed, and so the parameters determining the
value of the MOSCAP are the overlap, sidewall and fringe capacitance between
the gate and the drain or source. These
capacitances are only dependent on the width of the MOSCAP.
If
the MOSCAP is biased so that its’ channel is formed and it is at its’ max
capacitance value, this value is determined by the gate to channel capacitance
as well as the overlap, sidewall and fringe capacitance. The gate to channel capacitance is dependent
upon the area of the channel, or the MOSCAP’s width and length. Since we are interested in the ratio between
the max and min values of the MOSCAP, we can see that this ratio is dependent
only upon the length of the MOSCAP.
The
ratio of interest is max to min capacitance value, and the ratio is directly
dependent on the length. Increasing the length of the MOSCAP increases the max
to min capacitance ratio.
Figure 4: Illustration of the capacitances in a
MOSCAP.
The
design in Fig. 3 was simulated using HP EESof.
Fig. 5 shows the oscillator at its maximum frequency. Simulations of the PLL control input,
modulated data and digital frequency tuning were run also. The PLL and control and modulated data input
varied the oscillator frequency correctly with a low sensitivity. The digital tuning and negative resistance
control were also completely functional.
Figure 5: Simulation of the VCO using HP EESof.
A
design for a low sensitivity VCO was presented along with a discussion of its
place in a Bluetooth transmitter. A low
sensitivity VCO was possible because switched capacitance tuning reduced the
required tuning range of the VCO.
Performance considerations of the MOSCAPs used in the design were
discussed along with recommendations for sizing the capacitors. Simulation results using HP EESof were
shown.
Additional
students involved in the overall Bluetooth transceiver design have included
Jeff Boswell, Ryan Boyd, Ryan Dejmal, Brett Eller, Neal Huettenmueller, Sam
Johnson, Joel M. Krause, Jianming Li, Aaron Orsborn, Challapannair Nandakumar,
Kythakyapuzha R.Shobak, Isaac Stauffer, Travis Watson, Mike Wilson, and Jun
Zhang.
[1]
W. B. Kuhn, “Student-Designed Bluetooth Radio in Silicon-on-Sapphire,” IEEE RFIC Conf., 2001.
2]
Bluetooth SIG, http://www.bluetooth.com/,
Specification of the Bluetooth System, v
1.0B, 1999.
[3]
J. P. K. Gilb, “Bluetooth Radio Architectures,” IEEE RFIC Symposium,2000.
[4]
T.-H. Lin, W. J. Kaiser, “A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an
Automatic SC Tuning Loop,” IEEE J.
Solid-State Circuits, vol. 36, pp. 424-431, March 2001.
[5]
A. Kral, et. al., “RF-CMOS Oscillators with Switched Tuning,” IEEE Custom Integrated Circuits Conf., 1998,
pp. 555-558.
[6]
Peregrine Semiconductor, http://www.peregrine-semi.com/.