K-State's EECE765
Digital Radio Microelectronics Design Class
Spring 2002
 


 

Copyright 2002, Kansas State University

Information in these pages is the property of Kansas State University and the students involved in the class.
Please contact Dr. Kuhn for details on intellectual property restrictions
 



Course Overview

During the Spring 2002 semester, seven students at Kansas State University took part in EECE765 (Digital Radio Microelectronics Design) - an NSF-sponsored course covering the design of RF integrated circuits like those found in modern wireless products.  As in previous offerings, the class included traditional lecture/homework material, but also included project work during the latter part of the semester.
 



Project Goal

This semester's project involved refinement of a core technology being researched at K-State.  The class was divided into two 3-person teams plus a design consultant to develop competing realizations of on-chip bandpass filters and associated local oscillators operating at 2.4 to 2.5 GHz and 5.2 to 5.4 GHz.  These circuits will be used within the K-State Bluetooth receiver and transmitter architectures developed in previous offerings of the course.

The K-State Bluetooth receiver architecture employs a traditional superhet receiver together with a non-traditional front-end.  The front-end is composed of a Q-enhanced LNA and associated phase-locked local oscillator feeding an image-reject downconversion mixer.  The Q-enhanced LNA includes on-chip preselection/image filtering with a bandwidth of approximately 25 MHz at 2.5 GHz (50 MHz for the 5.3 GHz realization).  To achieve this narrow bandwidth, active circuits increase the base Q of an on-chip LC tank circuit from approximately 15 to approximately 100.  Practical considerations including noise figure/dynamic-range and real-time tuning of the filter are key issues being researched.
 

Top-Level Block Diagram

A block diagram of the design is shown in Figure 1 below.











Detailed Design

Students participating in the class were divided into three teams and worked together to produce the transmitter circuits.  Their designs, together with layouts and simulation results are detailed in the following pages:



Chip Layout, Fabrication, and Testing

Our design will be fabricated later this year in Peregrine's 0.5um Silicon-on-Sapphire process.  Test results will be posted here and documented in other publications after the fabricated chips are received.



Related Links
This material is based on work supported by the National Science Foundation under Grant No. ECS-9875770

Last Update:  10 May 2002