Negative Resistance and Frequency Tuning
These pages contains the description of the design and simulation results of the negative resistance cells and switched capacitor array. Both this circuits are used to improve and tune properties of the Q enhanced low noise amplifier (LNA). Negative resistance cells improves the Q factor of a resonant circuit, which determines bandwidth of an amplifier, and switched capacitor cells provides frequency tuning.

The requirements on negative resistance cells and switched capacitor array were derived from requirements on LNA and originates in bluetooth technical specifications. The negative resistance cells have to provide sufficient amount of negative resistance to allow the circuit oscillate (in oscillator part of the circuit) and also have to provide sufficiently fine step to allow precise setting of the final Q. Moreover, the negative resistance cell were supposed to have the ability of an analog tuning, which should increase the precision of a final Q setting even more. Switched capacitor array was required to provide sufficient tuning range of the resonant circuit in bandwidth used by bluetooth. This frequency tuning circuit was also required to have analog tuning ability, which in cooperation with a control circuitry would allow precise tuning control.
 
 
 


 

Fig. 1. Simplified schematic of  LNA with indicated blocks. Showed red blocks are discussed on this page.
Negative Resistance Cells

Negative resistance cells, supposed to eliminate positive resistance in LC resonant circuit, were required to meet following properties:

Total negative resistance needed for the oscillator                - 1 mS        (This requirement was derived from the given resistance of the LC tank circuit - 1kOhm)
Allow narrowing bandwidth of the Q enhanced LNA  to       20 MHz
 

Figure 2 shows the smallest negative resistance cell circuit, which contains several parts. Transistors T1 and T2 delivers negative resistance. They use the fact that the signals on the two signal busses contains the opposite AC voltages. This voltages are delivered to T1's and T2's gates through source followers T6 and T7, and control currents of drains, which are connected to the opposite signal busses than the gates. Thus, each time the voltage at a transistor's drain drops down the voltage at a transistor gate goes up, and so the transistor pulls more current. Pulling more drain current while the drain voltage decreases causes the circuit to have negative dynamic resistance. Transistors T3 and T4 provides ability of analog tuning. They allow the voltage drop between T1's and T2's gates and sources to decrease, and so lower the current these transistors pull. The voltage drop can be controlled by a voltage applied to T3's and T4's gates, which are the analog tuning control inputs. The source followers T6 and T7 improves the maximum voltage swing of the circuit. They allow the voltage on the signal busses to drop down, and still keep T1 and T2 in the active region. The transistor T5 can turn the cell on or off.
 


 

Fig. 2.  Minimal size negative resistance cell with indicated transistor sizing and bias voltages
The sizing of the transistors was based on following requirements. The smallest cell has to have it's negative resistance small enough to allow precise setting of the LNA bandwidth. Using the bandwidth precision requirement of 5 MHz, the sensitivity analysis provides that the smallest step should be 31.3uS. Trying to meet this requirement in the simulations, the outcomes showed that even with the minimum size of fets the circuits delivers slightly more negative resistance than required. This inconvenient has to be accepted; however, it doesn't decrease the bandwidth precision setting. The bandwidth can still be precisely set using analog tuning.
The analog tuning transistors design was based on the parameters of the IC process. Except of the precise bandwidth control, the analog tuning has to cover all 'gaps' between individual steps which can occur in the digital tuning. These gaps are dependent on the matching precision of the gm parameter, which I supposed to be 15%. Hence, when delivered negative resistance should be 1mS the analog tuning range has to be about 150uS. To meet this requirement not very sophisticated but working method of trial and error was used. During the simulation I came up with size of 8/0.5 of transistors T3 and T4, which in complete schematic delivered needed tuning range.
The source followers T6 and T7 used as voltage shifters has to enable the biggest voltage swing of the signal on the signal busses. The maximal voltage swing can be computed using following reflection. First, the voltage at the gates of T1 and T2 needs to be equal to treshlold voltage Vt plus maximum voltage Vm. Next, the difference between T1 and T2 gate voltage needs to be twice the maximum voltage swing minus the treshold voltage (This requirement is derived from state when one signal bus goes up by Vm and the second goes down by Vm, while the transistor T1 and T3 needs to be kept in the active region). Last, the signal busses has to be on a voltage level low enough to allow T6 and T7 to be in the active region even in case of maximum positive voltage swing. This requirement sets signal busses' voltage level Vs to Vcc + Vth - Vm.
Mathematically:

Vg = Vm +Vth
Vs - Vg = 2 Vm - Vth
Vs = Vcc + Vth - Vm

where Vg is voltage at the gate of T1 and T2, Vm is the maximum voltage swing, Vt. is the treshold voltage, Vg is voltage at signal busses, and Vcc is supply voltage. Substituting the first and the third equation to the second one, and solving for Vm, one can get:

Vm = (Vcc + Vth)/4 = 0.9V

Hence, the maximum voltage swing is approximately +-0.9V. Consequently this value determines Vg and Vs value, which are indicated in the schematic in Fig. 2.

Simulation Results

In the complete circuit, a 6 bit binary weighted array composed from the minimum negative resistance cell was used. An AC simulation, using signal with magnitude of 1V on signal busses, was run on it, while a current flowing into the negative resistance array was examined. Real part of this current corresponded to the provided negative resistance. Simulation first showed that when all the cells was turned on the maximum negative resistance (conductance) reached value of 2.68mS (Fig.3). Next, examination of a change in current when the least significant cell was turned on and off showed the smallest negative resistance step (Fig. 4.), which came out to be 41uS. That is somewhat more than required 31.3uS. Last, the simulation of the analog tuning range (Fig. 5) showed span of 161uS, in which the negative resistance can be changed continuously. This last simulation (and actually the previous one as well) was performed with the most significant bit of digital control set to zero, and so the overall negative resistance approximately set to the level of 1mS, which is around the value required to be in working circuit.
 
 


 

Fig. 3. Maximum negative resistance simulation. The figure shows real (red), imaginary (cyan), and absolute (blue) value of the current flowing through the negative resistance cells when all of them are turned on.  Because the applied voltage was 1V, the probed real part of the current - - 2.68mA - respond to the negative conductance of -2.68mS.

 
Fig. 4. Minimum negative resistance step simulation. The minimum step showed up to be 41uS, which is slightly more than required 31uS.
 

 
Fig. 5. Tuning range of analog negative resistance tuning. In this simulation the most significant bit was set to zero (the most significant cell array was turned off). The real part of the current (red color) shows the range of negative resistance tuning to be 161.9uS.
Frequency Tuning Cells

To accomplish frequency tuning ability of the designed LNA switched capacitor array was used. This array was built using MOS capacitors, which were turned on and of changing its gate to source voltage. The smallest component of the switched capacitor array - the smallest MOS cap cell - is showed in Fig. 6.
 
 

Fig. 6. The smallest MOS cap cell


Requirements on the frequency tuning was to provide frequency step smaller than 15MHz, and also to provide ability of analog frequency tuning, which in cooperation with PLL should accomplish precise LNA filter setting. Moreover, the frequency tuning circuitry should be able to tune within the range used by bluetooth; however, this is very weak requirement, because uncertainty in the actual value of the capacitance of MOS caps, is so big that the the tuning just needs to be as big as possible. These requirement determined minimum cell transistor sizing which is showed in the Fig. 6 (The actual size was found with help of the simulator), and also determined number of minimum cells - the 8 bit binary weighted array was used.
The analog tuning was accomplished using following circuit:
 

Fig. 7. Analog frequency tuning circuit
This circuit takes advantage of an area of MOS fet transistor between depletion and inversion region. In this area the capacitance gradually changes, and can by controlled by a gate to source voltage. The problem is that this region is very narrow - only a small change in voltage changes the capacitance completely. Therefore, to take the advantage of this area, the signal voltage had to be divided between several cell, each of which is composed of a MOS cap set between depletion and inversion region. The schematic in Fig. 7. shows the actual schematic used for analog tuning. Sizing of the transistors was based on requirement to cover any possible gaps in digital tuning. The biggest gap, dependent on matching precision, was supposed to be 5% of the biggest possible capacitance change. From, the other point of view, the analog tuning was supposed to be able to have a tuning range of 5% of the total frequency tuning ability. To meet this requirement, during the simulations, the sizing of the transistors and coupling capacitors was set as Fig. 7 shows. The number of  stages of the circuit was decided based on a need to have the highest number of stages possible (which decreases voltage on each stage, keeping it in the region between depletion and inversion) and not to have huge capacitors and transistors on a chip. 7 stages and capacitors with size of 1.5pF and transistors with size of 95/0.5 um seemed to be a good compromise.

Simulation Results

The frequency tuning was simulated using schematic in Fig. 1. The simulation - AC type - examined maximum frequency tuning range, minimum frequency step, and analog tuning range. The results are shown in Figures 8, 9, and 10.
 

Fig. 8. Maximum tuning range ability. The circuit is able to tune form 2GHz to 3GHz, which gives it a range of 1Ghz.


Fig. 9. Minimum digital tuning step. The circuit is able to move the LNA filter position by 5MHz.
 

 
Fig. 10. Analog frequency tuning range. The simulation showed a range of 50 MHz. (Well this is not the picture you are supposed to see. I've accidentally lost the original picture, replacing it with the previous one. When I wanted to run the simulation again, that silly simulator refused to start... so... at leas I'm giving you a picture which has a similar shape, but wrong range. Actual difference between these two peaks was about 5MHz. )
 Why Do I Believe This Circuit Might Work

Most of the design was based on effort to gain the biggest tuning ranges as possible. The last step in the design is to take a look whether these ranges are sufficient for the designed LNA. To summarize, the reached parameters of negative resistance and frequency tuning are

Maximum negative resistance                 -2.7 mS
Minimum negative resistance step            41 uS
Analog negative resistance tuning  range    162uS

Maximum frequency tuning range               2 GHz - 3 GHz     = frequency change of 1 GHz
Minimum frequency tuning step                  5 MHz
Analog frequency tuning range                     50 MHz
 
 

Proof that these parameters are sufficient is provided by sensitivity analysis.

For examination negative resistance circuit, following influences to positive resistance of inductor in the resonant circuit were supposed. First the temperature change from -40 to 60 degrees of Celsius. Second, 40% of uncertainty in a Q of the inductor (expected value is 15). These two influences, as sensitivity analysis showed, can wary a need of negative resistance from -500uS  to -1.5mS. This range is sufficiently covered by negative resistance circuit.

The frequency tuning circuit has to be able to deal with uncertainty of capacitance of used MOS caps. When 30% error is supposed the sensitivity analysis shows that tuning range should be at leas 835MHz. The tuning range of the used circuit is about 1GHz, and so it meets this requirement.