Objective: Perform a full design and implementation process for a Numerically Controlled Oscillator (NCO) in Verilog.
Steps:
1. Create the design of a NCO based on the discussion in class. The value of the NCO increment will be based on a 4-bit input (from DIP switches). The NCO should have a 26-bit width and active low asynchronous reset and enable inputs.
2. Write a testbench for the design and verify it’s functionality.
3. Synthesize the design for the Altera Flex10K, with a goal to run the clock for each design at 25.175 MHz. Look at the schematics and verify the synthesized design is what you expected. Save your output in EDIF, and Synopsys DB formats. You may make pin assignments during synthesis if desired.
4. Use Altera’s MaxPlusII to place and route the .edf file created by Synopsys.
5. Do a post-route simulation of your design to verify there are no timing problems.
6. Program a Flex10K20 on a UP-1 board in RA 295 and verify the circuit works as planned.
7. Have Dr. Gruenbacher verify your design is working (in the lab).
DUE: 4:30 pm, Monday, March 8, 2004
TURN IN:
1) Source file(s) and testbench
2) Synthesis scripts, area and timing reports for the design
3) A short summary of any problems you encountered, if any.
POINTS: 30
Synthesis Notes:
design_analyzer (X-Window version)
- Use Setup >> Command Window to see/execute shell commands
dc_shell (text version)
Performing synthesis requires a .synopsys_dc.setup file (available from templates directory)
Steps: (note: you may run synthesis commands from a script using the include command,
See an example script in the ~grue/vhdl/templates/clkadd/scripts directory)
1) analyze and elaborate design files using the read command
read –format vhdl source/design.vhd
2) uniquify any replicated components (only if you have multiple instantiations of the same lower-level design)
3) set constraints (timing and/or area)
a. create_clock
b. set_max_area
4) compile
5) generate reports (report_timing, report_area, check_design)
6) produce output files (Synopsys dB, EDIF, VHDL, Verilog, SDF)
a. the write command produces these files, use –f for the different formats
b. a Synopsys dB file is a database file that will store all design and compiler information. Consider it a way to save your project workspace.
Other useful commands from the command window:
1) help <command name>
2) current_design (similar to cd and pwd)
3) list_designs
4) report_reference, report_port, report_net, …
Example synthesis script:
read -format vhdl source/design.vhd
uniquify
create_clock -name "clk" -period 10 -waveform { "0" "5" } { "clk" }
compile -map_effort medium
check_design >> reports_rc_design.rpt
report_timing >> reports/rc_timing.rpt
report_area >> reports//rc_area.rpt
write ripple_ctr -hierarchy -output db/ripple_ctr.db
Remember, full documentation is available from
/usr/local/synopsys/doc/online/top.pdf
See www.eece.ksu.edu/~hdl/Tools/altera_synop.htm for directions on using Altera’s MaxPlusII with Synposys.
My project clkadd demonstrates most of these principles. It is located in ~grue/vhdl/templates/clkadd